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M54HC590
RAD-HARD 8 BINARY COUNTER REGISTER WITH 3 STATE OUTPUT
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HIGH SPEED: fMAX = 61 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4A(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) for QA ~ QH OUTPUT |IOH| = IOL = 4mA (MIN) for RCO OUTPUT BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 590 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9204-071
DILC-16
FPC-16
ORDER CODES
PACKAGE DILC FPC FM M54HC590D M54HC590K EM M54HC590D1 M54HC590K1
DESCRIPTION The M54HC590 is an high speed CMOS 8-BIT BINARY COUNTER REGISTER (3 STATE) fabricated with silicon gate C2MOS technology. This device contains an 8-bit binary counter that feeds an 8-bit storage register. The storage
register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR and a count enable input CCKEN. For cascading, a ripple carry output RCO is provided. Expansion is easily accomplished by tying RCO of the first stage to CCKEN of the second stage, etc. Both the counter and register clocks are positive edge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register. Internal circuitry prevents clocking from the clock enable. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION
June 2004
Rev. 1
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M54HC590
Figure 1: IEC Logic Symbols
Figure 2: Input And Output Equivalent Circuit
Table 1: Pin Description
PIN N 1, 2, 3, 4, 5, 6, 7, 15 11 12 13 9 14 10 8 16 SYMBOL QA to QH CCK CCKEN RCK RCO G CCLR GND VCC NAME AND FUNCTION Outputs Counter Clock Input Counter Clock Enable Input Register Clock Input Ripple Carry Output Output Enable Input Counter Clear Input Ground (0V) Positive Supply Voltage
Table 2: Truth Table
INPUTS OUTPUT G H L X X X X X X X X X X RCK X X CCLR X X X X L H H H CCKEN X X X X X L L H X CCK X X X X X Q OUTPUTS DISABLE Q OUTPUTS ENABLE COUNTER DATA IS STORED INTO REGISTER REGISTER STAGE IS NOT CHANGED COUNTER CLEAR ADVANCE ONE COUNT NO COUNT NO COUNT
X: Don't Care RCO = QA'*QB'*QC'*QD'*QE'*QF'*QG'*QH' (QA' to QH': INTERNAL OUTPUTS OF THE COUNTER)
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Figure 3: Logic Diagram
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Figure 4: Logic Diagram
This logic diagram has not be used to estimate propagation delays
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Figure 5: Timing Chart
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Table 3: Absolute Maximum Ratings
Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current per Output PIN (RCO) (QA - QH) Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 25 35 70 420 -65 to +150 265 Unit V V V mA mA mA mA mW C C
ICC or IGND DC VCC or Ground Current PD Tstg TL
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
Table 4: Recommended Operating Conditions
Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V C ns ns ns
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Table 5: DC Specifications
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOH High Level Output Voltage (for QA to QH Outputs) 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage (for RCO Output) 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage (for QA to QH Outputs) 2.0 4.5 6.0 4.5 6.0 II IOZ Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current 6.0 6.0 6.0 IO=-20 A IO=-20 A IO=-20 A IO=-4.0 mA IO=-5.2 mA IO=-20 A IO=-20 A IO=-20 A IO=-6.0 mA IO=-7.8 mA IO=20 A IO=20 A IO=20 A IO=4.0 mA IO=5.2 mA IO=20 A IO=20 A IO=20 A IO=6.0 mA IO=7.8 mA VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND TA = 25C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 0.1 0.1 0.1 0.26 0.26 0.1 0.5 4 1.9 4.4 5.9 4.13 5.63 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 0.1 0.1 0.1 0.33 0.33 1 5 40 Typ. Max. Value -40 to 85C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 0.1 0.1 0.1 0.40 0.40 1 10 80 A A A V V V V Max. -55 to 125C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage (for RCO Output)
VIL
V
VOH
ICC
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Table 6: AC Electrical Characteristics (CL = 50 pF, Input tr = tf = 6ns)
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 CL (pF) TA = 25C Min. Typ. 25 7 6 30 8 7 56 19 16 53 21 18 48 17 14 60 21 18 39 13 11 51 17 14 28 14 12 13 52 61 36 9 8 32 8 7 44 11 9 76 19 16 Max. 60 12 10 75 15 13 165 33 28 175 35 30 145 29 25 185 37 31 105 21 18 135 27 23 105 21 18 5.2 26 31 100 20 17 75 15 13 100 20 17 175 35 30 0 0 0 125 25 21 95 19 16 125 25 21 220 44 37 0 0 0 Value -40 to 85C Min. Max. 75 15 13 95 19 16 205 41 35 220 44 37 180 36 31 230 46 39 130 26 22 170 34 29 130 26 22 4.4 22 26 145 29 25 110 22 19 150 30 26 255 51 43 0 0 0 -55 to 125C Min. Max. 90 18 15 115 23 20 250 50 43 265 53 45 220 44 37 280 56 48 160 32 27 205 41 35 160 32 27 ns Unit
tTLH tTHL Output Transition Time tTLH tTHL Output Transition Time (RCO) tPLH tPHL Propagation Delay Time (CCK - RCO) tPLH Propagation Delay Time (CCLR - RCO)
50
50
ns
50
ns
50
ns
tPLH tPHL Propagation Delay Time (RCK - Q)
50
ns
150
ns
tPZL tPZH High Impedance Output Enable Time
50
RL = 1 K
ns
150
RL = 1 K
ns
tPLZ tPHZ High Impedance Output Disable Time fMAX Maximum Clock Frequency Minimum Pulse Width (CCK, RCK) Minimum Pulse Width (CCLR) Minimum Set-up Time (CCKEN CCK) Minimum Set-up Time (CCK - RCK) Minimum Hold Time
50
RL = 1 K 6.6 33 39
ns
50
MHz
tW(L) tW(H) tW(L)
50
ns
50
ns
ts
50
ns
ts(H)
50
ns
th
50
ns
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Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 CL (pF) TA = 25C Min. Typ. 28 7 6 Max. 75 15 13
Value -40 to 85C Min. Max. 95 19 16 -55 to 125C Min. Max. 110 22 19 ns Unit
tREM
Minimum Removal Time (CCLR)
50
Table 7: Capacitive Characteristics
Test Condition Symbol Parameter VCC (V) TA = 25C Min. Typ. 5 40 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF Unit
CIN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
Figure 6: Test Circuit
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1K or equivalent RT = ZOUT of pulse generator (typically 50)
SWITCH Open VCC GND
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Figure 7: Waveform - Propagation Delay, Minimum Pulse Width (f=1MHz; 50% duty cycle)
Figure 8: Waveform - Minimum Setup And Hold Time (f=1MHz; 50% duty cycle)
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Figure 9: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle)
Figure 10: Waveform - Minimum Setup And Hold Time (f=1MHz; 50% duty cycle)
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Figure 11: Waveform - Minimum Pulse Width, Removal Time (f=1MHz; 50% duty cycle)
Figure 12: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle)
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DILC-16 MECHANICAL DATA
mm. DIM. MIN. A a1 a2 B b b1 D E e e1 e2 F I K L 10.90 1.14 17.65 7.62 7.29 2.1 3.00 0.63 1.82 0.40 0.20 20.06 7.36 0.45 0.254 20.32 7.62 2.54 17.78 7.87 7.49 17.90 8.12 7.70 3.83 12.1 1.5 0.429 0.045 0.695 0.300 0.287 0.88 TYP MAX. 2.71 3.70 1.14 2.39 0.50 0.30 20.58 7.87 MIN. 0.083 0.118 0.025 0.072 0.016 0.008 0.790 0.290 0.018 0.010 0.800 0.300 0.100 0.700 0.310 0.295 0.705 0.320 0.303 0.151 0.476 0.059 0.035 TYP. MAX. 0.107 0.146 0.045 0.094 0.020 0.012 0.810 0.310 inch
0056437F
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FPC-16 MECHANICAL DATA
mm. DIM. MIN. A B C D E F G H L M N 0.38 6.0 18.75 0.33 0.38 4.31 22.0 0.43 6.75 9.76 1.49 0.102 8.76 0.127 8.89 1.27 0.43 0.48 0.015 0.237 0.738 0.013 0.015 0.170 0.867 0.017 TYP 6.91 9.94 MAX. 7.06 10.14 1.95 0.152 9.01 MIN. 0.266 0.384 0.059 0.004 0.345 0.005 0.350 0.050 0.017 0.019 TYP. 0.272 0.392 MAX. 0.278 0.399 0.077 0.006 0.355 inch
F
G
D
H
16
9
A
N
L
1
8
H
E
M
C
B
0016030E
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Table 8: Revision History
Date 01-Jun-2004 Revision 1 First Release Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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